Broadband radio frequency (RF) receivers that operate at high clock frequencies have relatively high power requirements Moreover, broadband RF receivers that implement mixing digital-to-analog converter (DAC) architectures also have relatively high power requirements due to, at least in part, the relatively high clock frequency, e.g., 3 GHz, that has been used to generate digital local oscillator (LO) signals for the receivers and the relatively large number of data lines (DAC bits) required to achieve a relatively high mixing DAC linearity In such RF receivers, the mixing DAC has included an RF transconductance section and a switching section. The RF transconductance section has included an input that received an RF signal and an output that provided an RF current signal The switching section has been coupled to the RF transconductance section and has included inputs that received bits associated with the digital LO signal, which has been provided at outputs of a direct digital frequency synthesizer (DDFS) based on a single frequency clock signal. The switching section has mixed the RF current signal with the digital LO signal to provide an analog output signal at an output of the switching section. The single frequency clock signal has set a sample rate for the digital LO signal, which has been based on a sampled sine wave. Unfortunately, RF receivers that employ a single high frequency clock signal to set a sample rate for a DDFS provided digital LO signal have relatively high power requirements.
What is need is a technique for reducing power consumption in an RF receiver that implements a mixing digital-to-analog converter (DAC) architecture.